#ifndef __PX_HW_H__
#define __PX_HW_H__

/*
 * Mediaswitch register addresses
 */
#ifndef DMATESTING
#define MsWrite(addr,d) ((*(volatile unsigned long *)(addr))=(d))
#define MsRead(addr) (*(volatile unsigned long *) (addr))
#else
#define MsWrite(addr,d) 
#define MsRead(addr) 0
#endif
/*
 * Mediaswitch register addresses
 */
#if 0
#ifdef __KERNEL__
#   define MSWITCH_BASE 0xFFD00000
#else
#   define MSWITCH_BASE 0x7FD00000
#endif
#endif

#ifndef NEW_MS_BASE_ADDR
#define NEW_MS_BASE_ADDR	0xf9800000
#endif
#ifndef OLD_MS_BASE_ADDR
#define OLD_MS_BASE_ADDR	0xffd00000
#endif

#define USR_NEW_MS_BASE_ADDR	0x79800000
#define USR_OLD_MS_BASE_ADDR	0x7fd00000

extern unsigned int ms_base_addr;
#define MSWITCH_BASE (ms_base_addr)

#define MS_SYSTEM_REGISTER   (MSWITCH_BASE)
#define MS_CONTROL_REGISTER (MSWITCH_BASE+4)
#define MS_CTL_REG (MSWITCH_BASE+4)
#define MS_STAT_REG  (MSWITCH_BASE+8)
#define MS_IM_REG (MSWITCH_BASE + 12)
#define MS_ISR_REG (MSWITCH_BASE + 16)

#define MS_HEIM_REG (MSWITCH_BASE + 20)
#define MS_HEIS_REG (MSWITCH_BASE + 24)
#define MS_I2C_REG (MSWITCH_BASE + 0x0100)

#define MS_VOUT_NEXT_ADDR_REG (MSWITCH_BASE + 0x0228)
#define MS_VOUT_NEXT_COUNT_REG (MSWITCH_BASE + 0x022c)
#define MS_VOUT_CUR_ADDR_REG (MSWITCH_BASE + 0x0268)
#define MS_VOUT_CUR_COUNT_REG (MSWITCH_BASE + 0x026c)

#define MS_VIN_NEXT_ADDR_REG (MSWITCH_BASE + 0x0200)
#define MS_VIN_NEXT_COUNT_REG (MSWITCH_BASE + 0x0204)
#define MS_VIN_CUR_ADDR_REG (MSWITCH_BASE + 0x0240)
#define MS_VIN_CUR_COUNT_REG (MSWITCH_BASE + 0x0244)

#define MS_EVT_NEXT_ADDR_REG (MSWITCH_BASE + 0x0218)
#define MS_EVT_NEXT_COUNT_REG (MSWITCH_BASE + 0x021C)
#define MS_EVT_CUR_ADDR_REG (MSWITCH_BASE + 0x0258)
#define MS_EVT_CUR_COUNT_REG (MSWITCH_BASE + 0x025C)

#define MS_AOUT_NEXT_ADDR_REG (MSWITCH_BASE + 0x0230)
#define MS_AOUT_NEXT_COUNT_REG (MSWITCH_BASE + 0x0234)
#define MS_AOUT_CUR_ADDR_REG (MSWITCH_BASE + 0x0270)
#define MS_AOUT_CUR_COUNT_REG (MSWITCH_BASE + 0x0274)

#define MS_AIN_NEXT_ADDR_REG (MSWITCH_BASE + 0x0208)
#define MS_AIN_NEXT_COUNT_REG (MSWITCH_BASE + 0x020C)
#define MS_AIN_CUR_ADDR_REG (MSWITCH_BASE + 0x0248)
#define MS_AIN_CUR_COUNT_REG (MSWITCH_BASE + 0x024C)

/* IDE scatter/gather DMA list channel (same as analog audio input in pre-MS4) */
#define MS4_IDESG_NEXT_ADDR_REG (MSWITCH_BASE + 0x0208)
#define MS4_IDESG_NEXT_COUNT_REG (MSWITCH_BASE + 0x020C)
#define MS4_IDESG_CUR_ADDR_REG (MSWITCH_BASE + 0x0248)
#define MS4_IDESG_CUR_COUNT_REG (MSWITCH_BASE + 0x024C)

#define MS_VBI_NEXT_ADDR_REG (MSWITCH_BASE + 0x0210)
#define MS_VBI_NEXT_COUNT_REG (MSWITCH_BASE + 0x0214)
#define MS_VBI_CUR_ADDR_REG (MSWITCH_BASE + 0x0250)
#define MS_VBI_CUR_COUNT_REG (MSWITCH_BASE + 0x0254)

#define MS_OSD_NEXT_ADDR_REG (MSWITCH_BASE + 0x0238)
#define MS_OSD_NEXT_COUNT_REG (MSWITCH_BASE + 0x023c)
#define MS_OSD_CUR_ADDR_REG (MSWITCH_BASE + 0x0278)
#define MS_OSD_CUR_COUNT_REG (MSWITCH_BASE + 0x027c)

#define MS_IDE_NEXT_ADDR_REG (MSWITCH_BASE + 0x0220)
#define MS_IDE_NEXT_COUNT_REG (MSWITCH_BASE + 0x0224)
#define MS_IDE_CUR_ADDR_REG (MSWITCH_BASE + 0x0260)
#define MS_IDE_CUR_COUNT_REG (MSWITCH_BASE + 0x0264)

/* Mediaswitch2 */
#define MS2_SYSTEM_REGISTER   (MSWITCH_BASE+0x1000)
#define MS2_CONTROL_REGISTER (MSWITCH_BASE+0x1004)
#define MS2_CTL_REG (MSWITCH_BASE+0x1004)
#define MS2_STAT_REG  (MSWITCH_BASE+0x1008)
#define MS2_IM_REG (MSWITCH_BASE+0x100c)
#define MS2_ISR_REG (MSWITCH_BASE+0x1010)

#define MS2_HEIM_REG (MSWITCH_BASE + 0x1014)
#define MS2_HEIS_REG (MSWITCH_BASE + 0x1018)

#define MS2_VSB_REG (MSWITCH_BASE + 0x1020)

#define MS2_ILXMT_REG (MSWITCH_BASE + 0x1030)
#define MS2_ILRCV_REG (MSWITCH_BASE + 0x1038)
#define MS2_STOTR_REG (MSWITCH_BASE + 0x1100)
#define MS2_CLKDIV_REG (MSWITCH_BASE + 0x1034)
#define MS2_PKTDLY_REG (MSWITCH_BASE + 0x1104)

#define MS2_I2C_REG (MSWITCH_BASE + 0x1100)

#define MS2_OSOUT_NEXT_ADDR_REG (MSWITCH_BASE + 0x1228)
#define MS2_OSOUT_NEXT_COUNT_REG (MSWITCH_BASE + 0x122c)
#define MS2_OSOUT_CUR_ADDR_REG (MSWITCH_BASE + 0x1268)
#define MS2_OSOUT_CUR_COUNT_REG (MSWITCH_BASE + 0x126c)

#define MS2_VIN_NEXT_ADDR_REG (MSWITCH_BASE + 0x1200)
#define MS2_VIN_NEXT_COUNT_REG (MSWITCH_BASE + 0x1204)
#define MS2_VIN_CUR_ADDR_REG (MSWITCH_BASE + 0x1240)
#define MS2_VIN_CUR_COUNT_REG (MSWITCH_BASE + 0x1244)

#define MS2_EVT_NEXT_ADDR_REG (MSWITCH_BASE + 0x1218)
#define MS2_EVT_NEXT_COUNT_REG (MSWITCH_BASE + 0x121C)
#define MS2_EVT_CUR_ADDR_REG (MSWITCH_BASE + 0x1258)
#define MS2_EVT_CUR_COUNT_REG (MSWITCH_BASE + 0x125C)

#define MS2_AOUT_NEXT_ADDR_REG (MSWITCH_BASE + 0x1230)
#define MS2_AOUT_NEXT_COUNT_REG (MSWITCH_BASE + 0x1234)
#define MS2_AOUT_CUR_ADDR_REG (MSWITCH_BASE + 0x1270)
#define MS2_AOUT_CUR_COUNT_REG (MSWITCH_BASE + 0x1274)

#define MS2_AIN_NEXT_ADDR_REG (MSWITCH_BASE + 0x1208)
#define MS2_AIN_NEXT_COUNT_REG (MSWITCH_BASE + 0x120C)
#define MS2_AIN_CUR_ADDR_REG (MSWITCH_BASE + 0x1248)
#define MS2_AIN_CUR_COUNT_REG (MSWITCH_BASE + 0x124C)

#define MS2_VBI_NEXT_ADDR_REG (MSWITCH_BASE + 0x1210)
#define MS2_VBI_NEXT_COUNT_REG (MSWITCH_BASE + 0x1214)
#define MS2_VBI_CUR_ADDR_REG (MSWITCH_BASE + 0x1250)
#define MS2_VBI_CUR_COUNT_REG (MSWITCH_BASE + 0x1254)

#define MS2_OSD_NEXT_ADDR_REG (MSWITCH_BASE + 0x1238)
#define MS2_OSD_NEXT_COUNT_REG (MSWITCH_BASE + 0x123c)
#define MS2_OSD_CUR_ADDR_REG (MSWITCH_BASE + 0x1278)
#define MS2_OSD_CUR_COUNT_REG (MSWITCH_BASE + 0x127c)

#define MS2_OSIN_NEXT_ADDR_REG (MSWITCH_BASE + 0x1220)
#define MS2_OSIN_NEXT_COUNT_REG (MSWITCH_BASE + 0x1224)
#define MS2_OSIN_CUR_ADDR_REG (MSWITCH_BASE + 0x1260)
#define MS2_OSIN_CUR_COUNT_REG (MSWITCH_BASE + 0x1264)

#define MS2_ILOUT_NEXT_ADDR_REG (MSWITCH_BASE + 0x1230)
#define MS2_ILOUT_NEXT_COUNT_REG (MSWITCH_BASE + 0x1234)
#define MS2_ILOUT_CUR_ADDR_REG (MSWITCH_BASE + 0x1270)
#define MS2_ILOUT_CUR_COUNT_REG (MSWITCH_BASE + 0x1274)

/* Mediaswitch4 */
/* Digital Video In 2. The hardware specs say it should be called 0, but
 * it is going to be 2 for the software (for backward compatibility with
 * old terminology)
 */
#define MS4_VIN2_NEXT_ADDR_REG   (MSWITCH_BASE + 0x1210)
#define MS4_VIN2_NEXT_COUNT_REG  (MSWITCH_BASE + 0x1214)
#define MS4_VIN2_CUR_ADDR_REG    (MSWITCH_BASE + 0x1250)
#define MS4_VIN2_CUR_COUNT_REG   (MSWITCH_BASE + 0x1254)

/* Digital Audio In 2. Same note as above */
#define MS4_AIN2_NEXT_ADDR_REG   (MSWITCH_BASE + 0x1218)
#define MS4_AIN2_NEXT_COUNT_REG  (MSWITCH_BASE + 0x121C)
#define MS4_AIN2_CUR_ADDR_REG    (MSWITCH_BASE + 0x1258)
#define MS4_AIN2_CUR_COUNT_REG   (MSWITCH_BASE + 0x125C)

/* Oslink in and out 2. Same note as above */
#define MS4_OSOUT2_NEXT_ADDR_REG   (MSWITCH_BASE + 0x1238)
#define MS4_OSOUT2_NEXT_COUNT_REG  (MSWITCH_BASE + 0x123C)
#define MS4_OSOUT2_CUR_ADDR_REG    (MSWITCH_BASE + 0x1278)
#define MS4_OSOUT2_CUR_COUNT_REG   (MSWITCH_BASE + 0x127C)

#define MS4_OSIN2_NEXT_ADDR_REG   (MSWITCH_BASE + 0x0210)
#define MS4_OSIN2_NEXT_COUNT_REG  (MSWITCH_BASE + 0x0214)
#define MS4_OSIN2_CUR_ADDR_REG    (MSWITCH_BASE + 0x0250)
#define MS4_OSIN2_CUR_COUNT_REG   (MSWITCH_BASE + 0x0254)



/*
** IDE_ERROR and IDE_FEATURE register located at the same address offset
** IDE_ERROR is accessed when doing pio read only
** IDE_FEATURE is accessed when doing pio write only
** IDE_STATUS and IDE_COMMAND registers located at the same address offset
** IDE_STATUS is accessed when doing pio read only
** IDE_COMMAND is accessed when doing pio write only
** IDE_SECTOR_NUMBER, IDE_CYLINDER_LOW, IDE_CYLINDER_HIGH, IDE_DEVICE_HEAD[3:0]
** can be used for Logical Block addressing (LBA[27:0])
*/
#define MS_IDE_DATA_REG (MSWITCH_BASE + 0x0400)
#define MS_IDE_ERROR_REG (MSWITCH_BASE + 0x0404)
#define MS_IDE_FEATURE_REG (MSWITCH_BASE + 0x0404)
#define MS_IDE_SECTOR_COUNT_REG (MSWITCH_BASE + 0x0408)
#define MS_IDE_SECTOR_NUMBER_REG (MSWITCH_BASE + 0x040c)
#define MS_IDE_CYLINDER_LOW_REG (MSWITCH_BASE + 0x0410)
#define MS_IDE_CYLINDER_HIGH_REG (MSWITCH_BASE + 0x0414)
#define MS_IDE_DEVICE_HEAD_REG (MSWITCH_BASE + 0x0418)
#define MS_IDE_STATUS_REG (MSWITCH_BASE + 0x041c)
#define MS_IDE_COMMAND_REG (MSWITCH_BASE + 0x041c)
#define MS_IDE_ALT_STATUS_REG (MSWITCH_BASE + 0x0438)
#define MS_IDE_DEV_CONTROL_REG (MSWITCH_BASE + 0x0438)
#define MS_IDE0_PIO_DATA_TIMING_REG (MSWITCH_BASE + 0x0500)
#define MS_IDE1_PIO_DATA_TIMING_REG (MSWITCH_BASE + 0x0504)
#define MS_IDE0_MWDMA_TIMING_REG (MSWITCH_BASE + 0x0508)
#define MS_IDE1_MWDMA_TIMING_REG (MSWITCH_BASE + 0x050c)
#define MS_IDE_PIO_COMMAND_TIMING_REG (MSWITCH_BASE + 0x0510)
#define MS_IDE_ULTRA_DMA_CONTROL_REG (MSWITCH_BASE + 0x0514)
#define MS_IDE0_ULTRA_DMA_TIMING_REG (MSWITCH_BASE + 0x0518)
#define MS_IDE1_ULTRA_DMA_TIMING_REG (MSWITCH_BASE + 0x051c)

/*
** Brooktree 865A Digital Video Encoder
** registers and address. NOTE THIS IS U233 ON PX hardware
*/


#define BT865_I2C_ADDR 0x8a
#define BT865_I2C_SRESET_REG 0xa6
#define BT865_I2C_ECCF2_REG 0xbc
#define BT865_I2C_ESTATUS_REG 0xce


#define BT865_ESTATUS_EACTIVE 0x2
#define BT865_ESTATUS_ECBAR   0x10
#define BT865_SRESET_SRESET   0x80
#define BT865_ECCF2_CBSWAP   0x2

/*
** IBM CS22 MPEG Audio Video Decoder
** registers and address.
*/
#define CS22_BASE (MSWITCH_BASE +  0x600)
#define CS22_CHIP_CONTROL    (CS22_BASE + (0x0<<2) )
#define CS22_CHIP_MODE       (CS22_BASE + (0x1<<2) )
#define CS22_VIDEO_FIFO      (CS22_BASE + (0x8<<2) )
#define CS22_VIDEO_FIFO_STAT (CS22_BASE + (0x9<<2) )
#define CS22_RB_THRESHOLD    (CS22_BASE + (0x2b<<2) )
#define CS22_COMMAND         (CS22_BASE + (0x0a<<2) )
#define CS22_CMD_DATA        (CS22_BASE + (0x0b<<2) )
#define CS22_CMD_STAT        (CS22_BASE + (0x0c<<2) )
#define CS22_CMD_ADDR        (CS22_BASE + (0x0d<<2) )
#define CS22_PROC_IADDR      (CS22_BASE + (0x0e<<2) )
#define CS22_PROC_IDATA      (CS22_BASE + (0x0f<<2) )
#define CS22_WR_PROT_IDATA   (CS22_BASE + (0x35<<2) )
#define CS22_HOST_INT        (CS22_BASE + (0x18<<2) )
#define CS22_INT_MASK        (CS22_BASE + (0x19<<2) )
#define CS22_HOST_INT1       (CS22_BASE + (0x3e<<2) )
#define CS22_INT1_MASK       (CS22_BASE + (0x3f<<2) )
#define CS22_AUD_IADDR       (CS22_BASE + (0x1a<<2) )
#define CS22_AUD_IDATA       (CS22_BASE + (0x1b<<2) )
#define CS22_AUD_FIFO        (CS22_BASE + (0x1c<<2) )
#define CS22_AUD_CTL         (CS22_BASE + (0x1d<<2) )
#define CS22_BEEP_CTL        (CS22_BASE + (0x1e<<2) )
#define CS22_FRNT_ATTEN      (CS22_BASE + (0x2d<<2) )
#define CS22_DISP_MODE       (CS22_BASE + (0x20<<2) )
#define CS22_DISP_DLY        (CS22_BASE + (0x21<<2) )
#define CS22_VBI_CTL         (CS22_BASE + (0x22<<2) )
#define CS22_DISP_LBOR       (CS22_BASE + (0x23<<2) )
#define CS22_DISP_TBOR       (CS22_BASE + (0x24<<2) )
#define CS22_INFC_CTL        (CS22_BASE + (0x2c<<2) )
#define CS22_OSD_ADDR        (CS22_BASE + (0x14<<2) )
#define CS22_OSD_DATA        (CS22_BASE + (0x15<<2) )
#define CS22_OSD_MODE        (CS22_BASE + (0x17<<2) )
#define CS22_OSD_LINK_ADDR   (CS22_BASE + (0x29<<2) )
#define CS22_OSD_SIZE        (CS22_BASE + (0x2a<<2) )
#define CS22_SYNC_STC2       (CS22_BASE + (0x02<<2) )
#define CS22_SYNC_STC1       (CS22_BASE + (0x03<<2) )
#define CS22_SYNC_STC0       (CS22_BASE + (0x04<<2) )
#define CS22_SYNC_PTS2       (CS22_BASE + (0x05<<2) )
#define CS22_SYNC_PTS1       (CS22_BASE + (0x06<<2) )
#define CS22_SYNC_PTS0       (CS22_BASE + (0x07<<2) )

#define CS22_DRAM_ADDRHI     (CS22_BASE + (0x10<<2) )
#define CS22_DRAM_ADDRLO     (CS22_BASE + (0x11<<2) )
#define CS22_DRAM_DATA       (CS22_BASE + (0x12<<2) )
#define CS22_DRAM_CTL        (CS22_BASE + (0x13<<2) )



#define CS22_AVSYNC_OFF 0x10
#define CS22_AVSYNC_VIDEO_MASTER 0x20
#define CS22_AVSYNC_AUDIO_MASTER 0x40
#define CS22_VIDEO_READY 0x2
#define CS22_VIDEO_RUN   0x3

/*
 * MediaSwitch Interrupt status register
 */

typedef enum {
  tyIdeNextEmpty = 1<<12,
  tyIdeIdle = 1<<4,
  
  tyVoutNextEmpty = 1<<13,
  tyVoutIdle = 1<<5,

  tyVinNextEmpty = 1<<8,
  tyVinIdle = 1<<0,  

  tyAoutNextEmpty = 1<<14,
  tyAoutIdle = 1<<6,

  tyAinNextEmpty = 1<<9,
  tyAinIdle = 1<<1,
  
  tyEvtNextEmpty = 1<<11,
  tyEvtIdle = 1<<3,

  tyVbiNextEmpty = 1<<10,
  tyVbiIdle = 1<<2,
  
  tyOsdNextEmpty = 1<<15,
  tyOsdIdle = 1<<7,
  
  tyVinNext

} TyIsrMasks;

typedef enum {
  tyOsinNextEmpty = 1<<12,
  tyOsinIdle = 1<<4,
  
  tyOsoutNextEmpty = 1<<13,
  tyOsoutIdle = 1<<5,

  tyVin2NextEmpty = 1<<8,
  tyVin2Idle = 1<<0,
  tyDigVin1NextEmpty = tyVin2NextEmpty,
  tyDigVin1Idle = tyVin2Idle,

#if 0
  tyAout2NextEmpty = 1<<14,
  tyAout2Idle = 1<<6,
#endif

  tyAin2NextEmpty = 1<<9,
  tyAin2Idle = 1<<1,
  tyDigAin1NextEmpty = tyAin2NextEmpty,
  tyDigAin1Idle      = tyAin2Idle,

  
  tyEvt2NextEmpty = 1<<11,
  tyEvt2Idle = 1<<3,

#if 0
  tyVbi2NextEmpty = 1<<10,
  tyVbi2Idle = 1<<2,
  
  tyOsd2NextEmpty = 1<<15,
  tyOsd2Idle = 1<<7,
#endif

  tyILinkOutNextEmpty = 1<<14,
  tyILinkOutIdle = 1<<6,

} TyIsrMasks2;

typedef enum {
  tyDigAin2NextEmpty = 1<<11,
  tyDigAin2Idle      = 1<<3,

  tyDigVin2NextEmpty = 1<<10,
  tyDigVin2Idle      = 1<<2,
  
  tyOsout2NextEmpty  = 1<<15,
  tyOsout2Idle       = 1<<7,

  tyOsin2NextEmpty   = 1<<10,
  tyOsin2Idle        = 1<<2,

  tyIdeSGNextEmpty = 1<<9,
  tyIdeSGIdle = 1<<1,

} TyIsrMasks4;

#endif
