/*
 * PowerPC memory management structures
 */

#ifndef _PPC_MMU_4xx_H_
#define _PPC_MMU_4xx_H_

/* Hardware Page Table Entry */
typedef struct _PTE
   {
      unsigned long rpn:22;     /* real page number */
      unsigned long ex:1;       /* executable page */
      unsigned long wr:1;       /* writable page */
      unsigned long zsel:4;	/* zone select */
      unsigned long w:1;	/* Write-thru cache mode */
      unsigned long i:1;	/* Cache inhibited */
      unsigned long m:1;	/* Memory coherence */
      unsigned long g:1;	/* Guarded */
   } PTE;

#define mkTLBHI(p) \
	((((unsigned long)p)&~0x3ff)|(0x7<<7)|(1<<6))

typedef struct _pte {
   	unsigned long page_num:20;
   	unsigned long flags:12;		/* Page flags (some unused bits) */
} pte;

#define PD_SHIFT (10+12)		/* Page directory */
#define PD_MASK  0x02FF
#define PT_SHIFT (12)			/* Page Table */
#define PT_MASK  0x02FF
#define PG_SHIFT (12)			/* Page Entry */
 
/* invalidate a TLB entry */
extern inline void _tlbie(unsigned long va)
{
	asm volatile ("tlbie %0" : : "r"(va));
}

extern inline void _tlbia(void)
{
	asm volatile ("tlbia" : : );
}

/* Number of TLB entries, and how many to reserve */
#define NTLB		64
extern int NTLB_WIRED;

#define TLBHI_EPN	0xfffffc00
#define TLBHI_PGSZ	0x380
#define		TLBHI_PGSZ_1K	0
#define		TLBHI_PGSZ_4K	(1 << 7)
#define		TLBHI_PGSZ_16K	(2 << 7)
#define		TLBHI_PGSZ_64K	(3 << 7)
#define		TLBHI_PGSZ_256K	(4 << 7)
#define		TLBHI_PGSZ_1M	(5 << 7)
#define		TLBHI_PGSZ_4M	(6 << 7)
#define		TLBHI_PGSZ_16M	(7 << 7)
#define TLBHI_VALID	0x40

#define TLBLO_RPN	0xfffffc00
#define TLBLO_PERM	0x300
#define 	TLBLO_EX	0x200
#define 	TLBLO_WR	0x100
#define TLBLO_ZSEL	0xf0
#define		TLBLO_Z_KERN	0
#define		TLBLO_Z_USER	0x10
#define TLBLO_ATTR	0xf
#define 	TLBLO_W		0x8
#define 	TLBLO_I		0x4
#define 	TLBLO_M		0x2
#define 	TLBLO_G		0x1

#endif
