/*
 * include/asm/s403_reg.h
 *
 * Copyright (C) 1992, 1994 by Theodore Ts'o.
 * 
 * Redistribution of this file is permitted under the terms of the GNU 
 * Public License (GPL)
 * 
 * These are the UART port assignments, expressed as offsets from the base
 * register.  These assignments are unique to the internal serial port of
 * the PowerPC 403 embedded processor
 */

#ifndef _LINUX_S403_REG_H
#define _LINUX_S403_REG_H

#define UART_SPLS	0	/* I/O:  Serial Port Line Status */
#define UART_RSVD1	1	/* Reserved */
#define UART_SPHS	2	/* I/O: Handshake status register */
#define UART_RSVD2	3	/* Reserved */
#define UART_BRDH	4	/* I/O: Baud Rate Divisor High */
#define UART_BRDL	5	/* I/O: Baud Rate Divisor Low */
#define UART_SPCTL	6	/* I/O: Ser Port Control */
#define UART_SPRC	7	/* I/O: Ser Port Receiver Command */
#define UART_SPTC	8	/* I/O: Ser Port Transmitter Command */
#define UART_SPRX	9	/* I: Ser Port Receive Buffer */
#define UART_SPRB	9	/* I: Ser Port Receive Buffer */
#define UART_SPTX	9	/* O: Ser Port Transmit Buffer */
#define UART_SPTB	9	/* O: Ser Port Transmit Buffer */

/* UART_SPCTL */
#define UART_SPCTL_LM_AUTOECHO	0x80 /* Auto Echo mode */
#define UART_SPCTL_LM_INTERNAL	0x40 /* Internal loopback mode */
#define UART_SPCTL_DTR		0x20 /* DTR Active */
#define UART_SPCTL_RTS		0x10 /* RTS Active */
#define UART_SPCTL_FRAME8	0x08 /* 8 bit data frames. If 0, 7 bit frames */
#define UART_SPCTL_PARITY	0x04 /* Parity enabled */
#define UART_SPCTL_PARODD	0x02 /* Odd parity, if 0, even. */
#define UART_SPCTL_STOP2	0x01 /* 2 stop bits, If 0, 1 stop bit */

/* UART_SPHS */
#define UART_SPHS_DIS		0x80 /* DSR Input Inactive Error */
#define UART_SPHS_CS		0x40 /* CTS Input Inactive Error */

/* UART_SPLS */
#define UART_SPLS_RBR		0x80 /* Receive Buffer Ready.  1 if full */
#define UART_SPLS_FE		0x40 /* Framing Error */
#define UART_SPLS_OE		0x20 /* Overrun Error */
#define UART_SPLS_PE		0x10 /* Parity Error */
#define UART_SPLS_LB		0x08 /* Line Break */
#define UART_SPLS_TBR		0x04 /* Transmit Buffer Ready. 1 if empty */
#define UART_SPLS_TSR		0x02 /* Transmit Shift Ready. 1 if empty */

#define UART_SPLS_CLRALL	0xF8

/* UART_SPRC */
#define UART_SPRC_ER		0x80 /* Enable Receiver */
#define UART_SPRC_DMA		0x40 /* DMA Mode */
#define UART_SPRC_DMA3		0x20 /* In DMA mode, use DMA channel 3 */
#define UART_SPRC_DMA2		0x00 /* In DMA mode, use DMA channel 2 */
#define UART_SPRC_RBR		0x20 /* In non-DMA mode, enable receive intr */
#define UART_SPRC_EIE		0x10 /* Enable error interrupts */
#define UART_SPRC_PME		0x08 /* Hardware control of RTS */

/* UART_SPTC */
#define UART_SPTC_ET		0x80 /* Enable transmitter */
#define UART_SPTC_DMA		0x40 /* DMA Mode */
#define UART_SPTC_DMA3		0x20 /* In DMA mode, use DMA channel 3 */
#define UART_SPTC_DMA2		0x00 /* In DMA mode, use DMA channel 2 */
#define UART_SPTC_TIE		0x20 /* Tx Empty Interrupt Enable */
#define UART_SPTC_TIE2		0x10 /* Tx Ready interrupt enable */
#define UART_SPTC_EIE		0x08 /* Tx Error Interrupt Enable */
#define UART_SPTC_SPE		0x04 /* Pause when CTS is inactive */
#define UART_SPTC_TB		0x02 /* Enable break charater */
#define UART_SPTC_PGM		0x01 /* Enable pattern generation */

#endif /* _LINUX_S403_REG_H */

